From: Ian Campbell <ian.campbell@citrix.com>
Date: Wed, 10 Jul 2013 10:54:00 +0000 (+0200)
Subject: arm: correct vfp save/restore asm constraints
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~6651
X-Git-Url: https://dgit.raspbian.org/%22http://www.example.com/cgi/success//%22http:/www.example.com/cgi/success/?a=commitdiff_plain;h=74d57ce43b2266b274ad89189ca3280c1e286883;p=xen.git

arm: correct vfp save/restore asm constraints

Some versions of gcc complain:
> vfp.c: In function 'vfp_restore_state':
> vfp.c:45:27: error: memory input 0 is not directly addressable
> vfp.c:51:31: error: memory input 0 is not directly addressable

There is no way to express the constraint we want (which is the address of the
array, clobbering the whole array). Therefore we have to fake it up by using
two constraints.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Will.Deacon@arm.com
Acked-by: Julien Grall <julien.grall@linaro.org>
---

diff --git a/xen/arch/arm/arm32/vfp.c b/xen/arch/arm/arm32/vfp.c
index 6780131c8c..0069acd297 100644
--- a/xen/arch/arm/arm32/vfp.c
+++ b/xen/arch/arm/arm32/vfp.c
@@ -22,15 +22,15 @@ void vfp_save_state(struct vcpu *v)
     }
 
     /* Save {d0-d15} */
-    asm volatile("stc p11, cr0, %0, #32*4"
-                 : "=Q" (v->arch.vfp.fpregs1));
+    asm volatile("stc p11, cr0, [%1], #32*4"
+                 : "=Q" (*v->arch.vfp.fpregs1) : "r" (v->arch.vfp.fpregs1));
 
     /* 32 x 64 bits registers? */
     if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 )
     {
         /* Save {d16-d31} */
-        asm volatile("stcl p11, cr0, %0, #32*4"
-                     : "=Q" (v->arch.vfp.fpregs2));
+        asm volatile("stcl p11, cr0, [%1], #32*4"
+                     : "=Q" (*v->arch.vfp.fpregs2) : "r" (v->arch.vfp.fpregs2));
     }
 
     WRITE_CP32(v->arch.vfp.fpexc & ~(FPEXC_EN), FPEXC);
@@ -38,17 +38,18 @@ void vfp_save_state(struct vcpu *v)
 
 void vfp_restore_state(struct vcpu *v)
 {
+    //uint64_t test[16];
     WRITE_CP32(READ_CP32(FPEXC) | FPEXC_EN, FPEXC);
 
     /* Restore {d0-d15} */
-    asm volatile("ldc p11, cr0, %0, #32*4"
-                 : : "Q" (v->arch.vfp.fpregs1));
+    asm volatile("ldc p11, cr0, [%1], #32*4"
+                 : : "Q" (*v->arch.vfp.fpregs1), "r" (v->arch.vfp.fpregs1));
 
     /* 32 x 64 bits registers? */
     if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 ) /* 32 x 64 bits registers */
         /* Restore {d16-d31} */
-        asm volatile("ldcl p11, cr0, %0, #32*4"
-                     : : "Q" (v->arch.vfp.fpregs2));
+        asm volatile("ldcl p11, cr0, [%1], #32*4"
+                     : : "Q" (*v->arch.vfp.fpregs2), "r" (v->arch.vfp.fpregs2));
 
     if ( v->arch.vfp.fpexc & FPEXC_EX )
     {